Qucs, also known as the Quite Universal Circuit Simulator, was developed as an affordable, open source, graphical, electronic circuit and loop simulator. The program supports all types of circuit simulation, such as DC, AC, S-parameters, harmonic balance analysis, noise analysis and so on. Simulation results can be viewed on the presentation page or program window.
Qucsator, the server part of the program, is a command-line simulator that manages a list of networks in a specific Qucs dataset I/O format. By default, it was created to work with the Qucs project, but it can also be used with other applications. The program supports exporting images of characters with Verilog-A files to C++ code, and supports direct communication with Verilog-HDL characters and VHDL trailers. The latest versions of Qucs have a GNU/Octave interface.
- Verilog-HDL and Verilog-A syntax support in text documents;
- support of C++ code export;
- support of equations for Verilog-HDL and VHDL subchains;
- pre-compiled VHDL modules and libraries;
- support for all modern components;
- open source allows for the development of extensions;
- customizable and extensible interface;
- a built-in file converter;
- the ability to download additional interface languages.